1. Field of the Invention
The present invention relates generally to network computing, data coding and encoding, and, in particular, to a global time and frequency distribution for optical or electronic packet-switching or burst-switching crossbar networks with synchronization-based error reporting and correction.
2. Description of Related Art
There is a need for a synchronous extension that offers advantages for clustered computing architectures. Synchronous processing is also desirable for cases where the data traffic comes in short bursts, since clock synchronization facilitates error detection and recovery.
A first problem with conventional crossbar switch interconnection systems is clock distribution and clock synchronization between the multiple line cards. As data is transmitted from each line card ingress element to each line card egress element, the circuits in each card must be clocked at identical frequencies to allow recovery of the data from the analog transmitted optical or electrical signal. In the past, this switch-global frequency distribution has been typically accomplished with a copper-distributed low-frequency oscillator, which is locally multiplied up to the higher data transmission frequency in each card. However, as data transmission bitrates rise to 10 Gb/s, 40 Gb/s, and even 100 Gb/s, a much better method for distributing a low-jitter, high precision clock across the system is needed.
A second problem with conventional crossbar switch interconnection systems is data integrity. As data transmissions rates rise above the 10 Gb/s level, there is increasing difficulty transmitting and receiving data without data errors. A more robust error detection and recovery method is needed. A standard method for error recovery is to label each packet of data with a unique identifying sequence number so that when a packet is corrupted, the destination can notify the source that the packet wasn't received. These sequence numbers and acknowledgment mechanisms require extra overhead that degrades the usable throughput of the network. There is a need for a globally distributed and synchronized clock mechanism for allowing error detection and recovery without the overhead of sequence numbers and explicit packet acknowledgments.